With the recent advancement of digital technologies, there has been a trend toward processing or storing a large amount of data at high speed. There thus has been a demand for a semiconductor device with a high degree of integration and a high level of performance for use in electronic equipment.
To meet such a demand, in order to achieve a high degree of integration for a semiconductor memory device, e.g., DRAM (Dynamic Random Access Memory), research and development is recently in progress popularly for using a ferroelectric material or a high-permittivity material to a capacitor insulating film of the capacitor element configuring the DRAM as alternatives to silicon oxide and silicon nitride that have been previously used. Such a semiconductor memory device includes a flash memory and a ferroelectric memory (FeRAM), which are each a nonvolatile memory not losing stored information even if power is turned off.
The FeRAM is provided with a floating gate, and stores information in the floating gate by the accumulation of charge being the representation of the information, for example. The floating gate is embedded in a gate insulating film of an Insulated Gate Field Effect Transistor (IGFET). With such a configuration of the FeRAM, for writing and erasing of information, there needs to provide a flow of tunnel current to pass through the insulating film, thereby requiring a relatively high level of voltage. Moreover, for operating a readable/writable nonvolatile RAM with a lower level of voltage at a higher speed, research and development is actively in progress for using, as a capacitor insulating film, a ferroelectric film having spontaneous polarization characteristics.
The FeRAM performs storage of information utilizing the hysteresis characteristics of the ferroelectric material used to configure the ferroelectric capacitor. The ferroelectric capacitor is of a configuration in which a ferroelectric film is sandwiched between a pair of electrodes, i.e., upper and lower electrodes. Such a ferroelectric capacitor is known to exhibit polarization depending on the level of voltage applied to the electrodes, and exhibit spontaneous polarization even if the voltage application is stopped. Accordingly, information can become available for reading therefrom by detecting inversion of the spontaneous polarization as a result of inversion of the applied voltage. Such a FeRAM operates with a lower level of voltage compared with a flash memory, thereby enabling high-speed writing with lower power consumption. In the previous logic technology, a FeRAM-combined logic chip (SOC: System On Chip) has been recently under study for use with an IC card, for example.
There is also a demand for the FeRAM to have a much higher degree of integration and a much higher level of performance, and the reduction of a cell area is expected to be required from now on. For the reduction of a cell area, adopting the stack configuration as an alternative to the previous planar configuration is known to be effective. Note here that, in the stack configuration, a capacitor is formed directly above a plug, i.e., contact plug, formed on the drain of a transistor configuring a memory cell.
In a FeRAM of the previous stack configuration, a ferroelectric capacitor is configured by laminating a barrier metal, a lower electrode, a ferroelectric film, and an upper electrode in this order directly above a conductive plug made of W (tungsten). The barrier metal serves to prevent oxidation of the conductive plug. The barrier metal and the lower electrode are generally formed by a combination of two or more films selected from a TiN film, a TiAlN film, an Ir film, an IrO2 film, a Pt film, and an SRO (SrRuO3) film.
The ferroelectric film configuring the ferroelectric capacitor in the FeRAM is formed by a lead zirconate titanate (PZT), a Bi layer-structured compound such as SrBi2Ta2O9 (SBT, Y1), SrBi2 (Ta, Nb)2O9 (SBTN, YZ), Bi4T13O9, (Bi, La)4Ti3O12, and BiFeO3, or others. Such a ferroelectric film is formed by a sol-gel method, sputtering, and Metal Organic Chemical Vapor Deposition (MOCVD), for example.
For increasing the electrical characteristics of a ferroelectric memory such as FeRAM, and for increasing the product yield thereof, the film made of the ferroelectric material needs to be controlled to ensure a uniform crystal orientation thereof. Such crystal orientation of the ferroelectric film is largely affected by the crystal orientation of the lower electrode. Accordingly, if the lower electrode is ensured to have a uniform crystal orientation, the ferroelectric film can be also ensured to have a uniform crystal orientation. As such, in order to manufacture a ferroelectric memory with improved electrical characteristics and a high product yield, a uniform crystal orientation of the lower electrode is needed.
The lower electrode of a previous ferroelectric capacitor of the stack configuration is known to be in a lamination structure of Pt, IrO2, and Ir in this order from above. Such a technology is described in Japanese Laid-open Patent Publication No. hei09-22829, for example.
For improving the crystallinity of the lower electrode, forming a lamination structure of Ir, Iro, Pt, PtO, and Pt in this order from below has been also under study. The technology related thereto is found in Japanese Laid-Open Patent Publication No. 2003-92391, and in Japanese Laid-open Patent Publication No. 2004-153006, for example. With such a lamination structure, the Ir film is preferably formed with the thickness of 200 nm or thicker for preventing oxidation of a conductive plug. With such a thick Ir film, however, etching will become difficult.
For increasing the stability against oxygen, a study has been made to use precious metal such as Ir, IrOx, Pt, Pd, PdOx, and Au, or conductive oxide for the lower electrode, and to form the lower electrode with the film thickness of about 30 nm to 100 nm. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-318371, for example.
Another type of capacitor is known to have a lamination structure including a lower electrode formed on a contact layer, a first dielectric film formed on the lower electrode, a floating electrode formed on the first dielectric film, a second dielectric film formed on the floating electrode with a different orientation direction from the first dielectric film, and an upper electrode formed on the second dielectric film. With such a structure, the contact layer is exemplified by those made of TiOx, Pt, Ti, PtOx, IrOx, ZrOx, TiN, TiAlN, and others. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-209179, for example.
The lower or upper electrode may be of a lamination structure with a plurality of films. The lamination structure in this case includes a selective layer, e.g., oxygen barrier layer, an oxygen-source layer, e.g., conductive oxide film, a precious-metal film, or a conductive oxide film, for example. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2000-357777.
An electrode with high adhesion properties is known to have a lamination structure including a first conductive film (IrO), a second conductive film (Ir) formed on the first conductive film, and a third conductive film (Pt) formed on the second conductive film. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2000-91539, for example. Another lamination structure is also developed, i.e., a conductive plug is formed thereon with, in this order, an adhesive film (Ti), a diffusion barrier film (e.g., Ir, or Ru), a metal oxide film (IrO2, RuO2, LSCO, and SRO), and a heat-resistance metal film (Ir, Pt, Ru, Rh, Os, and Pa). The technology related thereto is found in Japanese laid-open Patent Publication No. 2001-111007, for example.
Another type of lamination structure is also known, i.e., an oxygen barrier film is laminated on a lower electrode for preventing diffusion of oxygen. Such a lamination structure is IrO2/Ir/TiAlN/TiN, for example. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2005-159165, for example. The lower electrode is also known to have a lamination structure of TiAlN, Ti, and Pt in this order. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2004-95638, for example. Note here that when a film of Ir is used to an electrode, the fatigue properties with a film of PZT (lead zirconate titanate) formed on the electrode are affected better compared with the film of Pt formed on the electrode. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2000-164818, for example.
With the lamination structure of a lower electrode, it is considered preferable to include at least an Ir layer like Ir/Pt/Ir, Ir/Pt, or Pt/Ir. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-298136, for example.
For the purpose of preventing oxidation of a conductive layer configuring a lower electrode, the conductive film may be formed thereon with a precious-metal film, and the precious-metal film may be formed thereon with a strong feeder film. The precious-metal film in this case is formed to be in a lamination structure of at least two or more layers. The technology related thereto is found in Japanese Laid-open Patent Publication No. hei11-145418, for example.
A dielectric capacitor is known to be manufactured by forming a Pt-made lower electrode film on a contact film, by forming a dielectric film on the lower electrode film, and then by forming an upper electrode on the dielectric film. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2002-151662, for example. Herein, when a diffusion barrier film made of a metallic substance is formed between the lower electrode film and the dielectric film, any possible diffusion of elements can be prevented therebetween. The technology related thereto is found in Japanese Laid-open Patent Publication No. hei06-326270, for example.
A semiconductor memory device is known to be a capacitor element in which a conductive plug is provided to an interlayer insulating film formed on a semiconductor substrate, and an electrode for connection to the conductive plug is formed on the interlayer insulating film. The electrode is provided with an iridium oxide film for use as an oxygen barrier film. This iridium oxide film is configured by a plurality of layers varying in average particle diameter of crystal. For example, among a plurality of layers configuring the iridium oxide film, any of those located upper may so set as to have the average crystal particle diameter of ½ or smaller than the film thickness thereof, and to have the average crystal particle diameter smaller than that of the other layers therebeneath. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-51583, for example.
As an alternative lamination structure, a lower electrode may be configured by an oxide layer, and the oxide layer is formed thereon with a metal film made of Ir or Ru. The metal film made of Ir or Ru may be formed thereon again with another oxide layer. The technology related thereto is found in Japanese Laid-open Patent Publication No. hei11-243179, for example. A previous electrode is of a lamination structure of any or some of Pt, Ir, Ru, IrO2, and RuO2, or a mixture thereof. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2005-108876, for example.
When a lower insulating film is formed between a lower conductive film and a dielectric film, a leak current of the dielectric film can be reduced to a further degree. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-264187, for example. As another lamination structure, it is known to perform sputtering to an IrOx film on an Ir film for use as a lower electrode before annealing it in an oxygen atmosphere, and form a PZT film thereon. In this case, the Ir film is formed with a temperature of 450° C. or higher, and the IrOx film is formed with a temperature equal to or lower than the temperature of forming the Ir film, e.g., 300° C. or higher. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2003-68991, for example.
For forming the PZT film, a lower electrode of IrO2 or others may be formed first, and then the resulting structure may be subjected to rapid thermal annealing (RTA). By annealing the lower electrode in an inert atmosphere, the PZT (111) film can be improved in intensity of orientation and switching charge (Qsw). The technology related thereto is found in Japanese Laid-open Patent Publication No. 2000-91551, for example.
Note here that, for forming the IrO2 film of the lower electrode, it is known that the Qsw is affected by a partial pressure ratio between an iridium flux and oxygen. The technology related thereto is found in Japanese Laid-open Patent Publication No. 2000-91270, for example.
For manufacturing a ferroelectric memory with satisfactory electrical characteristics with a high product yield, the crystal orientation of the ferroelectric material needs to be made uniform. The problem here is that, however, if a ferroelectric film is formed by MOCVD, the resulting ferroelectric film becomes susceptible to the influence of other layers therebeneath in terms of crystal orientation.